It is well known that the drive currents of metal-oxide-semiconductor (MOS) devices are affected by the stresses applied on their channel regions. The stresses in the channel regions may improve the carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type MOS (NMOS) device, and to induce a compressive stress in the channel region of a p-type MOS (PMOS) device.
Although the beneficial stresses in the channel regions are generally desirable, it is also realized that the magnitude of the drive current improvement is related to the magnitude of the stress. On a same semiconductor chip, the MOS devices may be applied with stresses having different magnitudes. Accordingly, the drive current improvements for different MOS devices may be different, resulting in non-uniform drive currents, and hence non-uniform drive current drifts.
The performance of MOS devices needs to be predictable, so that at circuit design time, simulations may accurately reflect the circuit behavior. Accordingly, it is preferred that in a semiconductor chip at least the MOS devices of a same type and in a same type of circuits have a uniform performance. However, with the non-uniform drive current drift, during the simulations of the circuit design, the drive current drift has to be compensated for. What makes the compensation of the drive current drift complicated is that the stresses of MOS devices are affected by various factors and those factors behave differently for different layouts.
Conventional integrated circuit designs, however, often neglected such an issue. For example, U.S. Pat. No. 5,278,105 provides a method for adding dummy regions. The method includes extracting layouts of active layers, forming blocked regions including the patterns of the active layers, and laying out dummy patterns in regions other than the blocked regions. FIG. 1 illustrates a possible layout including active regions 2, 4 and 6, gate electrode strips 8, 10 and 12, and dummy active regions 14. Active region 2 and the overlying gate electrode strip 8 belong to MOS device 18, while active region 4 and the overlying gate electrode strip 10 belong to MOS device 20. It is noted that one of the dummy active regions 14 is spaced apart from active region 2 by spacing S1. Accordingly, the paths for applying stress (referred to as stress-application paths hereinafter) by STI regions 16 have a length S1. On the other hand, along another stress-application path, the stress-application path may have length S2. The significant difference in the lengths of the stress-application paths results in a large variation in the stresses applied by STI regions 16, and hence in a significant variation in the performance (for example, drive currents) of MOS devices 18 and 20. For example, with a greater stress-application length S2, STI regions 16 may apply a greater stress to the channel region of MOS device 20 than the stress applied to the channel region of MOS device 18. The device drive current drift between MOS devices 18 and 20 may reach about 10 to 20 percent. Accordingly, new methods for reducing the drive current drifts of MOS devices are needed.